Ultra low-power energy recovery and clock gating schemes for multiplier

1. Introduction

Energy recovery is a technique originally developed for low power digital circuits. Energy recovery circuits achieve low energy dissipation by curtailing the current across devices with low electromotive force bead and by recycling the energy stored on capacitances by utilizing an AC type ( hovering ) supply electromotive force. The major part of entire power in extremely synchronal systems is dissipated on the clock web. Hence, energy recovery clocking is an effectual low power solution. In this method the clock is a resonating sinusoidal signal that recycles the energy from the clock web electrical capacities to the supply electromotive force. Replacing the conventional square moving ridge clock signal with a sinusoidal one requires alterations in the design of the reversals. Recently new reversals have been developed to run with energy recovery clock signals.Clock gating [ 1 ] is another popular technique for cut downing clock power.

Even though energy recovery timing consequences in significant decrease in clock power, there still remains some energy loss on the flip-flops themselves due to non-adiabatic exchanging [ 5 ] . Hence, it is still desirable to use clock gating to the energy recovery clock for farther cut downing the flip-flop power during idle periods. The bing clock gating solutions are based on dissembling the local clock signal utilizing dissembling logic Gatess ( NAND/NOR ) .These methods of clock gating do non work for energy recovery timing. This is because interpolation of dissembling logic Gatess eliminates energy recovery from the staying electrical capacities in downstream fan-out. To the best of our gating solutions proposed for the energy recovery timing. In my undertaking, I propose clock gating by modifying the design of the bing energy recovery clocked reversals to integrate a power salvaging characteristic that eliminates any energy loss on the internal clock and other nodes of the somersault floating-point operations.

Using the proposed clock gating technique to the flip-flops reduces their power by a significant sum during the sleep manner. Furthermore, the added characteristic has negligible power and hold operating expense when reversals are in the active manner. We besides designed an energy recovery clock generator [ 2 ] that maintains its oscillation amplitude under procedure and temperature fluctuations.

II. ENERGY RECOVERY FLIP-FLOPS

In this subdivision, my proposed reversals, every bit good as the conventional energy recovery reversal, [ 1 ] are presented and their operations are discussed.

The first proposed energy recovery reversal, Sense Amplifier Energy Recovery ( SAER ) [ 4 ] reversal, is shown in Figure 3. This reversal, which is based on the sense amplifier reversals proposed is a dynamic flip-flop with precharge and evaluate stages of operation. In this reversal is used to run with a low-tension swing clock. We use this reversal to run with an energy recovery clock. When the clock electromotive force exceeds the threshold electromotive force of the clock transistor ( MNl ) , rating occurs. At the oncoming of rating, the difference between the differential information inputs ( D and DB ) is amplified and either SET or RESET switches to low and is captured by the reset latch. The SET and RESET nodes are precharged high when the clock electromotive force falls below Vdd- Vth, where Vth is the threshold electromotive force of the precharging transistors ( MP1 and MP2 )

Although the SAER reversal is fast and uses reasonably low power at high informations exchanging activities, its chief drawback is that either the SET or RESET node is ever charged and discharged every rhythm, irrespective of the information activity. This leads to significant power

ingestion at low informations shift activities where the information is non altering often. I consider two attacks to turn to this job. One attack is to utilize a inactive reversal, and the other is to use conditional capturing

Since the clock inverter is skewed for fast high-to-low passages, the conducting period occurs merely during the lifting passage of the clock, but non on the falling passage. In this manner, an inexplicit conducting pulsation is generated during each lifting passage of the clock. A cascade of three inverters alternatively of one can give a somewhat sharper falling border for the upside-down clock ( CLKB ) . However, due to the slow rise nature of the energy recovery clock, adequate hold can be generated by a individual inverter. when the province of the input informations is the same as its province in the old conductivity stage, there are no internal passages. Therefore, power ingestion is minimized for low informations exchanging activities.

The 2nd attack for minimising flip-flop power at low informations shift activities is to utilize conditional capturing to extinguish excess internal passages. Figure 5 shows the Differential Conditional-Capturing Energy Recovery ( DCCER ) flip-flop [ 6 ] . Similar to adynamic reversal, the DCCER flip-flop operates in a precharge and evaluate manner. However, alternatively of utilizing the clock for precharging, little pull-up PMOS transistors ( MPI and MP2 ) are used for bear downing the precharge nodes ( SET and RESET ) . The DCCER flip-flop uses a NAND-based Set/Reset latch for the storage mechanism.

The conditional capturing is implemented by utilizing feedback from the end product to command transistors MN3 and MN4 in the rating waies. Therefore, if the province of the input informations is same as that of the end product, SET and RESET are non discharged. . Therefore, a reasonably big transistor is used for MN1. Furthermore, since there are four stacked transistors in the rating way, important charge sharing may happen when three of them become ON at the same time. Having decently sized pull-up PMOS transistors ( MP1 and MP2 ) alternatively of clock controlled precharge transistors ensures a changeless way to Vdd, which helps to cut down the consequence of charge sharing.

III. ENERGY RECOVERY CLOCK GATING

As opposed to square moving ridge clocking, the clock gating can non be implemented by interpolation of dissembling logic Gatess at any arbitrary node on the clock web. That is because interpolation of such logic Gatess on a sinusoidal clock web destroys the form of the clock and eliminated the energy recovery belongings in the downstream fan out electrical capacities of the clock web. Here, I propose a different attack to time gating of energy recovery clock by infixing the gating characteristic inside flip-flops themselves ( Fig. below ) .There are two constituents of power dissipation in flop-flops: clock circuit power ( power of logic Gatess connected to the clock ) and data circuit power ( power of the remainder of the flip-flop circuit ) .

I separated the clock circuit power from the information circuit power in our power measurings. Disabling the clock circuit ( inverter Gatess connected to the clock input in Fig. 5 in the idle province can extinguish both the clock circuit and informations circuit power. Hence, disabling of the inverter gates is the proposed attack to implementing clock gating inside energy recovery clocked flip-flops Fig. 5 shows SCCER with clock gating. Clock gating was implemented by replacing the inverter with the NOR gate. The NOR gate has two inputs. the clock signal and the enable signal. In the active manner, the enable signal is low so the NOR gate behaves merely like an inverter and the flip-flop operates merely like the original reversal. In the idle province, the enable signal is set to high which disables the internal clock by puting the end product of the NOR gate to be zero. This turns off the pull down way ( MN2 ) and prevents any rating of the information. Hence, non merely the internal clock is stopped ( clock power salvaging ) but besides all the internal shift is prevented ( power salvaging on informations circuits ) .

The energy recovery clock generator is a single-phase resonant clock generator as shown in Fig.8. Transistor M1 receives a mention pulsation to pull-down the clock signal to land when the clock reaches its lower limit ; thereby keeping the oscillation of the resonant circuit. This transistor is reasonably big, and hence, driven by a concatenation of increasingly sized inverters. The end product wave form of resonating energy recovery clock generator as shown in fig.9

IV. SIMULATION RESULT AND COMPARISONS

The proposed reversals are compared with the FPTG reversal. For single flip-flop simulations, an ideal sinusoidal clock was used. All the reversals were designed and laid-out utilizing TSMC 0.25- & A ; Icirc ; ?m procedure engineering with a supply electromotive force of 2.5 V. The designs were optimized at a temperature of 25 C for a clock frequence of 200 MHz. Figure below shows power as a map of informations exchanging activity for different reversals. The SAER reversal has the lowest power ingestion at high exchanging activities ; Figure 10 shows that different somersaults flop with power dissipation

IV. Decision

In my undertaking four novel energy recovery flip-flops that enable energy recovery from the clock web, ensuing in important entire energy nest eggs compared to the square-wave clocking. The proposed reversals operate with a single-phase sinusoidal clock, which can be generated with high efficiency. The consequences demonstrate the feasibleness and effectivity of the energy recovery timing strategy in cut downing entire power ingestion

V. REFERENCES

[ 1 ] Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy “ Energy Recovery Clocking Scheme and Flip Flops for Ultra Low-Energy Applications ” in Proc. Int. Symp. Low Power Electron. Des. , Aug. 2003, pp. 54-59.

[ 2 ] Tirumalashetty and H. Mahmoodi, “ Clock gating and negative border triping for energy recovery clock, ” in Proc. IEEE Int. Symp. Circuits Syst. , Aug. 2001, pp. 1141-1144..

[ 3 ] B. Nikolic, V. G. Oklobdzija, V. Stojanovic, J. Wenyan, J. Kar-Shing Chiu, and M. Ming-Tak Leung, “ Improved sense-amplifier-based flipflop: Design and measurings, ” IEEE J. Solid-State Circuits, vol. 35, pp. 876-884, Jun. 2000.

[ 4 ] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Ying- Chin Chou, “ Low-power digital systems based on adiabatic-switching rules, ” IEEE Trans. Very Large Scale Integr. ( VLSI ) Syst. , vol. 2, no. 4, pp. 398-407, Dec. 1994

[ 5 ] B. S. Kong, S.-S. Kim, and Y.-H. Jun, “ Conditional-capture reversal for statistical power decrease, ” IEEE J.Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, Aug. 2001